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Texas Instruments pushes Keystone towards supercomputers

Six new SoCs show how far TI wants to expand beyond base stations, targeting servers of various sizes plus industrial control


Published: 13 November, 2012

READ MORE: Texas Instruments | Infrastructure | Semiconductor

When Texas Instruments unveiled its Keystone system-on-chip architecture, it was clear that the brand new platform was designed to expand TI's reach beyond its traditional stronghold in base stations. How far it aims to stretch is more surprising though - after predictably pushing further into network processors and small cells earlier this year, it is now targeting servers as well as a wide range of networking gear with its combination of multicore ARM processors, DSPs and accelerators.

Marvell and start-up Calxeda have led the way into using ARM-based processors in servers, mainly addressing low power blade servers for cloud providers. TI also sees the shift to cloud architectures as its key driver, but is looking right up to high performance servers and supercomputers. Here, it is not aiming to oust the incumbent Intel x86 architecture, says Tom Flanagan, director of technical strategy at TI's wireless unit. Rather, it will offer chips to offload heavy duty floating point tasks, a role in which it will take on Nvidia, which makes a similar play, though using its graphics processing units rather than a DSP-based solution like TI's. Target functions would include media processing, video analytics and industrial imaging and control.

Flanagan believes the open ecosystem of ARM will ensure its success in many markets, especially if chip vendors stick with a unified approach - unlike some ARM users such as Qualcomm and Apple, TI uses the standard core design rather than adapting it, and relies on its accelerator and software efficiency to deliver a performance differential. The biggest of the new chips use up to four A15 cores and six DSPs to deliver up to 352GMACs and 19,600 Dhrystone MIPS.

Distinguishing features of its Keystone chips include a 256-bit interface from the cores to the SoC, clocked at the full 1.4GHz data rate of the cores, while some rivals use 128-bit interfaces clocked at only 33% to 50% of that rate. TI also squeezes up to 18Mbytes of aggregate memory on its top end SoCs and says it is unique in supporting Gigabit and 10Gbit Ethernet MACs.

The last of these features is critical to its positioning. Integrating networking onto the chip is a popular topic among chip designers as servers need to take on far greater levels of real time data analysis and other tasks where information must be processed in parallel and at ultra-high speeds. However, TI is rolling out 10Gbit capabilities imminently while Intel, for instance, is talking about 100Gbit networks-on-a-chip, but with no timelines. But adding integrated networking to a DSP/ARM architecture, in real world products, may allow TI to succeed in its aim of getting DSPs into servers.

While the high end server models will get the most attention, only two are devoted to that space. Another two come with just one DSP core and are aimed at smaller machines with less heavy signal processing loads, while two low end variants will focus on networking and industrial networks and come with no DSPs. These lower end chips will ship in the second half of next year while their high end stablemates are sampling from next month.

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